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Statements

Subject Item

dbr:Load–store_architecture

rdfs:label

Load–store architecture

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In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.

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dbc:Computer_architecture

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n10:Load–store_architecture?oldid=1055341673&ns=0

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35161236

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2056

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1055341673

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dbr:Register–memory_architecture dbr:Instruction_set_architecture dbr:Graphics_processing_unit dbc:Computer_architecture dbr:Computer_engineering dbr:Arithmetic_logic_unit dbr:Load–store_unit dbr:ARM_architecture_family dbr:Complex_instruction_set_computer dbr:Processor_register dbr:Reduced_instruction_set_computer dbr:X86 dbr:Vector_processor dbr:RISC-V dbr:CDC_6600 dbr:SPARC dbr:PowerPC dbr:Computer_memory dbr:MIPS_architecture

dbo:abstract

In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register-memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.

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n10:Load–store_architecture