About: Load-link/store-conditional

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In computer science, load-linked/store-conditional (LL/SC), sometimes known as load-reserved/store-conditional (LR/SC), are a pair of instructions used in multithreading to achieve synchronization. Load-link returns the current value of a memory location, while a subsequent store-conditional to the same memory location will store a new value only if no updates have occurred to that location since the load-link. Together, this implements a lock-free atomic read-modify-write operation. "Load-linked" is also known as load-link, load-reserved, and load-locked.

Attributes	Values
rdf:type	place
rdfs:label	Load-link/store-conditional (en)
rdfs:comment	In computer science, load-linked/store-conditional (LL/SC), sometimes known as load-reserved/store-conditional (LR/SC), are a pair of instructions used in multithreading to achieve synchronization. Load-link returns the current value of a memory location, while a subsequent store-conditional to the same memory location will store a new value only if no updates have occurred to that location since the load-link. Together, this implements a lock-free atomic read-modify-write operation. "Load-linked" is also known as load-link, load-reserved, and load-locked. (en)
sameAs	Load-link/store-conditional Load-link/store-conditional
dbp:wikiPageUsesTemplate	dbt:Citation_needed dbt:Cite_book dbt:Cite_journal dbt:Clarify dbt:Refbegin dbt:Refend dbt:Reflist dbt:Which dbt:More_footnotes_needed dbt:Cite_techreport
Subject	Concurrency control Programming constructs Transactional memory
gold:hypernym	Pair
prov:wasDerivedFrom	http://en.wikipedia.org/wiki/Load-link/store-conditional?oldid=1042059899&ns=0
Wikipage page ID	2882985 (xsd:integer)
page length (characters) of wiki page	10919 (xsd:nonNegativeInteger)
Wikipage revision ID	1042059899 (xsd:integer)
Link from a Wikipage to another Wikipage	Load–store architecture Non-blocking algorithm Processor register Skip list X86 ABA problem ARC (processor) ARM architecture family Big O notation Binary search tree Thread (computing) C/C++ Users Journal CPU cache Concurrency control Programming constructs Transactional memory Double compare-and-swap Java Development Kit PowerPC Power ISA DEC Alpha Linearizability Compare-and-swap Complex instruction set computer Computer science Task switching Micro-operation Synchronization (computer science) Faith Ellen Instruction pipelining Instruction set architecture Transactional memory National Atmospheric Release Advisory Center MIPS architecture RISC-V Read–modify–write Reference counting dbr:Chromatic_tree
has abstract	In computer science, load-linked/store-conditional (LL/SC), sometimes known as load-reserved/store-conditional (LR/SC), are a pair of instructions used in multithreading to achieve synchronization. Load-link returns the current value of a memory location, while a subsequent store-conditional to the same memory location will store a new value only if no updates have occurred to that location since the load-link. Together, this implements a lock-free atomic read-modify-write operation. "Load-linked" is also known as load-link, load-reserved, and load-locked. LL/SC was originally proposed by Jensen, Hagensen, and Broughton for the S-1 AAP multiprocessor at Lawrence Livermore National Laboratory. (en)
foaf:isPrimaryTopicOf	http://en.wikipedia.org/wiki/Load-link/store-conditional
is Wikipage redirect of	Load-Link/Store-Conditional Lwarx Llsc Load-Linked/Store-Conditional Stwcx LL/SC LR/SC
is Link from a Wikipage to another Wikipage of	Load-Link/Store-Conditional Non-blocking algorithm Non-blocking linked list Lwarx ABA problem Atomicity (database systems) Double compare-and-swap Linearizability Compare-and-swap Consensus (computer science) Microcontroller Llsc Load-Linked/Store-Conditional Fetch-and-add Instruction set architecture LL/SC LR/SC
is foaf:primaryTopic of	http://en.wikipedia.org/wiki/Load-link/store-conditional

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