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In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.

Attributes	Values
rdfs:label	Load–store architecture (en)
rdfs:comment	In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach. (en)
dbp:wikiPageUsesTemplate	dbt:Better_source dbt:Reflist dbt:Rp dbt:Comp-eng-stub
Subject	Computer architecture
prov:wasDerivedFrom	http://en.wikipedia.org/wiki/Load–store_architecture?oldid=1055341673&ns=0
Wikipage page ID	35161236 (xsd:integer)
page length (characters) of wiki page	2056 (xsd:nonNegativeInteger)
Wikipage revision ID	1055341673 (xsd:integer)
Link from a Wikipage to another Wikipage	Load–store unit Processor register X86 ARM architecture family Arithmetic logic unit CDC 6600 Computer architecture PowerPC Complex instruction set computer Computer engineering Computer memory SPARC Graphics processing unit Instruction set architecture Vector processor MIPS architecture RISC-V Reduced instruction set computer Register–memory architecture
has abstract	In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register-memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach. (en)
foaf:isPrimaryTopicOf	http://en.wikipedia.org/wiki/Load–store_architecture
is Wikipage redirect of	Load-store architecture Load/store architecture
is Link from a Wikipage to another Wikipage of	Load-link/store-conditional Load-store architecture Load/store architecture Load–store unit NEC V60 ARM architecture family Asynchronous circuit CDC 6000 series Glossary of computer hardware terms Java virtual machine DLX Clipper architecture Comparison of instruction set architectures Complex instruction set computer High-level language computer architecture Microarchitecture Minimal instruction set computer Data General Nova ILLIAC IV Idempotence HP Saturn Hardware acceleration Infineon TriCore Instruction set architecture Latency oriented processor architecture MIPS architecture MasPar
is foaf:primaryTopic of	http://en.wikipedia.org/wiki/Load–store_architecture

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