About: Latency oriented processor architecture

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Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on.

Attributes	Values
rdfs:label	Latency oriented processor architecture (en)
rdfs:comment	Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on. (en)
sameAs	Latency oriented processor architecture
dbp:wikiPageUsesTemplate	dbt:Efn dbt:Main dbt:Notelist dbt:Page_needed dbt:Reflist dbt:Short_description
Subject	Microprocessors
prov:wasDerivedFrom	http://en.wikipedia.org/wiki/Latency_oriented_processor_architecture?oldid=1068474792&ns=0
Wikipage page ID	51623894 (xsd:integer)
page length (characters) of wiki page	12916 (xsd:nonNegativeInteger)
Wikipage revision ID	1068474792 (xsd:integer)
Link from a Wikipage to another Wikipage	Load–store architecture Locality of reference Non-volatile memory Thread (computing) Throughput CAS latency CPU cache Cache (computing) Central processing unit Microprocessors Pipeline (computing) Computer data storage Microarchitecture Microprocessor Operand forwarding Data dependency Graphics processing unit Execution unit Hazard (computer architecture) Instruction-level parallelism Instructions per cycle Streaming SIMD Extensions Latency (engineering) MMX (instruction set) Video RAM (dual-ported DRAM) Re-order buffer Reduced instruction set computer Reservation station Single instruction, multiple data Single instruction, single data
has abstract	Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on. (en)
foaf:isPrimaryTopicOf	http://en.wikipedia.org/wiki/Latency_oriented_processor_architecture
is Link from a Wikipage to another Wikipage of	Computer performance
is foaf:primaryTopic of	http://en.wikipedia.org/wiki/Latency_oriented_processor_architecture

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